Terms
N-well: an N-type well diffused on a substrate; P-well: a P-type well diffused on a substrate; N+: an N-type heavily doped area; P+: a P-type heavily doped area; Fox: a field oxide layer; and Pbody: a P-type doped body area.
An MOS transistor is an elementary unit constituting a semiconductor integrated circuit and constituted of a well, a source, a drain and a gate, and polysilicon is typically used as the gate of the MOS transistor in the semiconductor integrated circuit, i.e., a polysilicon gate.
In some types of integrated circuits, e.g., some BCD integrated circuits (Bipolar-Complementary MOS-Power Dual Diffusive MOS integrated circuits), two layers of polysilicon are included and both of them act as gates of an MOS transistor, which are referred respectively to as a first layer of polysilicon gate and a second layer of polysilicon gate.
A structure of a dual-layer polysilicon gate will be introduced below taking a BCD integrated circuit as an example as illustrated in FIG. 1.
In FIG. 1, two MOS transistors in a BCD integrated circuit, i.e., a low voltage NMOS and a power LDNMOS are depicted. A first layer of polysilicon gate (the poly-Si 1 in FIG. 1) is a gate of the power LDNMOS, and a second layer of polysilicon gate (the poly-Si 2 in FIG. 1) is a gate of the low voltage NMOS, where a thick oxide layer is indicated as Fox. The area covered by the Fox is a field area, and the area which is not covered by the Fox is an active area with the surface thereof being a thin oxide layer of gate oxide. The gate oxide beneath the poly-Si 1 and the poly-Si 2 is referred respectively to as a first layer of gate oxide and a second layer of gate oxide. N+ is a source and a drain of the MOS transistor, and Pbody is a body area of the power LDNMOS.
In the prior art, a method of manufacturing the dual-layer polysilicon gate is as illustrated in FIG. 2:
The step 201 is to manufacture an N-well and a P-well on a substrate (see FIG. 3);
The step 202 is to manufacture an active area and a field area (see FIG. 4 where the area covered by the Fox is a field area, and the area which is not covered by the Fox is an active area);
The step 203 is to grow a first layer of gate oxide on the active area (see FIG. 5);
The step 204 is to deposit a first layer of polysilicon, and perform a photolithographic process on and etch the first layer of polysilicon to form a first layer of polysilicon gate (see FIG. 6, i.e., the poly-Si 1 in FIG. 6);
The step 205 is to dope the Pbody (see FIG. 7);
The step 206 is to perform lower-pressure chemical vapor deposition of silicon oxide (LPTEOS) (see FIG. 8);
The step 207 is to sinter the Pbody at high temperature (see FIG. 9);
The step 208 is to wet-etch silicon oxide (see FIG. 10);
The step 209 is to grow a second layer of gate oxide (see FIG. 11);
The step 210 is to deposit a second layer of polysilicon (see FIG. 12); and
The step 211 is to perform a photolithographic process on and etch the second layer of polysilicon to form a second layer of polysilicon gate (see FIG. 13, i.e., the poly-Si 2 in FIG. 13).
After the foregoing steps are performed, the dual-layer polysilicon gate has been manufactured, and all the other steps are standard processes known to those skilled in the art, e.g., manufacture of N+ and P+ heavily doped areas (see FIG. 14).
The inventors have identified during making of the invention at least the following two drawbacks that are difficult to overcome in the foregoing manufacturing method: first, in the step 208, silicon oxide is wet-etched by eroding the bared LPTEOS and first layer of gate oxide using diluted hydrofluoric acid, and the gate oxide layer beneath the poly-Si 1 will not be eroded due to shielding by polysilicon, but the first layer of gate oxide at the edges of the poly-Si 1 may be easily damaged by the eroding solution, thus degrading the reliability of the device; and second, in the step 211, the area reserved for the second layer of polysilicon gate is covered by photoresist, and the photoresist in the other area is not reserved, and then the poly-Si 2 in the area which is not covered by the photoresist is etched in a dry etching process, and next the photoresist is removed, and this etching method makes the thickness of the poly-Si 2 in the area of the sidewalls of the poly-Si 1 (particularly the longitudinal thickness referred to as d1 in FIG. 12 here and throughout the following description) much larger than the thickness d2 of the poly-Si 2 in the planar area, thus making the etching process rather difficult.